Programmable logic devices (“PLDs”) exist as a well-known type of integrated circuit (“IC”) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (“PLAs”) and complex programmable logic devices (“CPLDs”). One type of programmable logic device, called a field programmable gate array (“FPGA”), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (“CLBs”) and programmable input/output blocks (“IOBs”). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (“bitstream”) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. CLBs and IOBs form the programmable part of an FPGA referred to as the “FPGA fabric”, which is subject to program control of the configuration memory cells.
CLBs and IOBs may be interconnected via widely distributed on-chip (“global”) routing resources or regionally specific on-chip (“local”) routing resources of an FPGA, such as one or more traces. Moreover, both global and local resources may be used to distribute signals, such as clock signals. A global routing resource may be programmatically coupled to another global routing resource or a local routing resource, or a local routing resource may be programmatically coupled to another local routing resource using what is known as a programmable interconnect point (“PIP”). Conventionally, PIPs have been programmed or reprogrammed using an externally provided configuration bitstream to program programmable logic. Some other types of circuitry that may be included in an FPGA are transceivers, digital clock managers (“DCMs”), and memory controllers.
DCMs may be programmed for providing any of a variety of clock signals. For example, clock signals of different frequencies or different phase relationships may be provided from a reference clock input to a DCM. Furthermore, DCMs may be programmed for providing such a variety of clock signals. Conventionally, DCMs have been programmed or reprogrammed using an externally provided configuration bitstream to program programmable logic.
In addition to configuration memory cells, groups of system memory cells, sometimes referred to as block random access memories (“BRAMs”), may be included in an FPGA. Like configuration memory cells, such BRAMS conventionally are formed using a standard six transistor (“6T”) static random access memory (“SRAM”) memory cell. However, known forms of either or both static and dynamic random access memory (“DRAM”) memory cells, as well as magnetoresistive random access memory cells (“MRAM”) and flash memory cells, may be included in FPGAs. Conventionally configuration memory cells, as well as system memory cells, were programmed and reprogrammed using an externally provided configuration bitstream.
FPGAs include transceivers, which may be configured for “single-ended” or “differential” signaling. A more recent trend is to provide high-speed transceivers, such as multi-gigabit transceivers (“MGTs”). Transceivers may be programmed to conform to any of a variety of communication standards by programming communication signaling parameters, such as duty cycle, frequency, and preemphasis, among other known communication signaling parameters. Conventionally, transceivers were programmed and reprogrammed using an externally provided configuration bitstream.
Accordingly, it should be appreciated that there are many circuits in a programmable logic device that may be programmed to provide user defined functionality. Furthermore, modern day programmable logic devices may include one or more other devices, such as one or more digital signal processors and microprocessors, among other known integrated circuit devices. For example, microprocessors may be embedded cores (“hard processors”) or programmed into CLBs (“soft processors”). While instructions for such other devices may reside in embedded memory, such as one or more BRAMs, such other devices were subject to there surroundings, namely, configuration of functional blocks programmed or reprogrammed using an externally provided configuration bitstream.
As mentioned above, conventionally an FPGA is programmed by supplying an external bitstream to configure the FPGA. Classically, once an FPGA was configured, it was seldom reconfigured, including without limitation configuration of resources previously not programmed, during operation. This had at least in part to do with having a relatively slow internal access port (“ICAP”) for reconfiguration. Notably, it should be appreciated that an ICAP conventionally may be used to configure or reconfigure an FPGA, as such an ICAP has access to all of the FPGA fabric for purposes of configuration or reconfiguration. However, an ICAP port runs at approximately one-third or less the frequency of which the FPGA may be run. Further impacting the ability to quickly achieve reconfiguration, an ICAP port has a minimum bit reconfiguration “granularity” of one frame. Thus, for example, if only one bit in a 1296 bit frame had to be changed, all 1296 bits were processed to change the one bit.
Accordingly, it would be desirable and useful to provide an integrated circuit having internal dynamic reconfiguration capability that is substantially faster than that afforded by an ICAP.